2M x 36, 2M x 32, 4M x 18 72 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.39163 Mbytes 页数：39 Pages

ISSI

矽成半导体

2M x 36, 2M x 32, 4M x 18 72 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.39163 Mbytes 页数：39 Pages

ISSI

矽成半导体

2M x 36, 2M x 32, 4M x 18 72 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.39163 Mbytes 页数：39 Pages

ISSI

矽成半导体

2M x 36, 2M x 32, 4M x 18 72 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.39163 Mbytes 页数：39 Pages

ISSI

矽成半导体