IS49NLC93200A-25EWBLI中文资料矽成半导体数据手册PDF规格书

FEATURES

 533MHz DDR operation (1.067 Gb/s/pin data rate)

 38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency)

 Reduced cycle time (15ns at 533MHz)

 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total, each 32ms)

 8 internal banks

 Non-multiplexed addresses (address multiplexing option available)

 SRAM-type interface

 Programmable READ latency (RL), row cycle time, and burst sequence length

 Balanced READ and WRITE latencies in order to optimize data bus utilization

 Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.