IS46DR81280D中文资料北京矽成数据手册PDF规格书

FEATURES

• Standard Voltage: Vdd and Vddq = 1.8V ±0.1V

• Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V

• SSTL_18-compatible for Standard Voltage

• SSTL_15-compatible for Low Voltage

• Double data rate interface: two data transfers per clock

cycle

• Differential data strobe (DQS, DQS)

• 4-bit prefetch architecture

• On chip DLL to align DQ and DQS transitions with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported

• Programmable CAS latency (CL) 3, 4, 5, 6, 7, 8 and 9

supported

• Posted CAS and programmable additive latency (AL)

0, 1, 2, 3, 4, 5 and 6 supported

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength, full and reduced

strength options

• On-die termination (ODT)

OPTIONS

• Configuration(s):

128Mx8 (16Mx8x8 banks)

64Mx16 (8Mx16x8 banks)

• Package:

x8: 60-ball BGA (8mm x 10.5mm)

x16: 84-ball WBGA (8mm x 12.5mm)

• Timing – Cycle time

1.8ns @CL=7 DDR2-1066F

2.2ns @CL=6 DDR2-900E

2.5ns @CL=5 DDR2-800D

• Temperature Range:

Commercial (0°C ≤ Tc ≤ 85°C)

Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C)

Tc = Case Temp, Ta = Ambient Temp

DESCRIPTION

ISSI's 1Gb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O balls.