Package：60-TFBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PARALLEL 60TFBGA

ISSI, Integrated Silicon Solution Inc

32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：652.68 Kbytes 页数：30 Pages

ISSI

矽成半导体

32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：652.68 Kbytes 页数：30 Pages

ISSI

矽成半导体

32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：652.68 Kbytes 页数：30 Pages

ISSI

矽成半导体

32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：652.68 Kbytes 页数：30 Pages

ISSI

矽成半导体