16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：776.64 Kbytes 页数：34 Pages

ISSI

矽成半导体

Auto Refresh and Self Refresh Modes

文件：1.0063 Mbytes 页数：33 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：776.64 Kbytes 页数：34 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：776.64 Kbytes 页数：34 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：776.64 Kbytes 页数：34 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) • VDD and VDDQ: 2.5V ± 0.1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver •

文件：776.64 Kbytes 页数：34 Pages

ISSI

矽成半导体

DDR SDRAM

·Single supply voltage of 2.5V or 2.6V\n·Standard double-data rate clock timing\n·SSTL_2 compatible inputs\n·Four internal banks with bank controls\n·Data masking per byte on Write commands\n·Programmable burst length of 2, 4, or 8\n·Programmable CAS Latency of 2, 2.5 or 3\n·Auto-Refresh Mode and Se

ISSI

矽成半导体