Internal bank for hiding row access/precharge

文件：1.57364 Mbytes 页数：66 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

文件：1.57007 Mbytes 页数：66 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

文件：1.57007 Mbytes 页数：66 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

文件：1.57007 Mbytes 页数：66 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

文件：1.57007 Mbytes 页数：66 Pages

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

文件：1.57007 Mbytes 页数：66 Pages

ISSI

矽成半导体

SDR SDRAM

·Synchronous, with 3.3V power supply\n·LVTTL interface\n·Programmable burst length (1, 2, 4, 8, full page)\n·Programmable burst sequence: Sequential/Interleave\n·Self refresh and Auto Refresh modes\n·Random column address every clock cycle\n·Programmable CAS latency (2, 3 clocks)\n·Burst read/write

ISSI

矽成半导体

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

ISSI, Integrated Silicon Solution Inc

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

ISSI, Integrated Silicon Solution Inc

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

ISSI, Integrated Silicon Solution Inc