4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

文件：895.21 Kbytes 页数：60 Pages

ISSI

矽成半导体

Package：86-TFSOP（0.400"，10.16mm 宽）；包装：管件 类别：集成电路（IC） 存储器 描述：IC DRAM 128MBIT PAR 86TSOP II

ISSI, Integrated Silicon Solution Inc

Package：86-TFSOP（0.400"，10.16mm 宽）；包装：管件 类别：集成电路（IC） 存储器 描述：IC DRAM 128MBIT PAR 86TSOP II

ISSI, Integrated Silicon Solution Inc

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

文件：895.21 Kbytes 页数：60 Pages

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

文件：895.21 Kbytes 页数：60 Pages

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

文件：895.21 Kbytes 页数：60 Pages

ISSI

矽成半导体