64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

文件：913.2 Kbytes 页数：61 Pages

ISSI

矽成半导体

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

ISSI, Integrated Silicon Solution Inc

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

ISSI, Integrated Silicon Solution Inc

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

文件：913.2 Kbytes 页数：61 Pages

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

文件：913.2 Kbytes 页数：61 Pages

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

文件：913.2 Kbytes 页数：61 Pages

ISSI

矽成半导体