IR3Y48A1中文资料夏普数据手册PDF规格书

DESCRIPTION

The IR3Y48A1 is a CMOS single-chip signal processing IC for CCD area sensors which includes correlated double sampling circuit (CDS), clamp circuit, programmable gain amplifier (PGA), reference voltage generator, black level detection circuit, 18 MHz 10-bit analog-to-digital converter (ADC), timing generator for internally required pulses, and serial interface for internal function control and PGA gain control.

FEATURES

• Low power consumption : 80 mW (TYP.)

• Wide gain range : –1.94 to 36 dB (Gain step : 0.047 dB/step)

• High speed sample-and-hold circuits : pulse width 11 ns (MIN.)

• Independent CDS and PGA gain control

– CDS : –1.94/0/6/12 dB

– PGA : 0 to 24 dB

• Black level canceler

– Settling target : 16 to 127 LSB

• Capable of independent input of ADC conversion clock and data output clock

• Power down mode : less than 1 mW

• Built-in serial interface

• 10-bit ADC operating up to 18 MHz

– DNL : ±0.6 LSB (TYP.)

• Maximum input level of CCD signals : 1.1 Vp-p

• Accepts a direct signal input to ADC or PGA

(input level : 1.0 Vp-p (TYP.))

• Single 2.7 to 3.6 V power supply

• Package :

48-pin QFP* (P-QFP048-0707) 0.5 mm pin-pitch

*Contact SHARP in order to obtain the details of package dimensions of the IR3Y48A1.