特征
Compliant with DisplayPort specification version 1.2 and_Embedded DisplayPort (eDP) specification version 1.3.
Support 2 Main Link Lanes at either 1.62Gb/s or 2.7Gb/s link rate
Support analog RGB output for VGA with Triple 9-bit DAC up to 200MHz pixel rate. Sync signals can be provided in separated or composite manner. Support VESA and_CEA timing standards up to 1920x1200@60Hz or 2048x1152@60Hz with reduced blanking
VGA output is compliant with VESA VSIS v1r2 specification
Embedded MCU to handle the control logic
Support device boot up by automatically loading firmware from on-chip flash Boot ROM
Integrated EDID Buffer， and_MCCS bypass supported
Supports Enhanced Framing Mode
Fast and_full Link Training for embedded DisplayPort system
Support eDP Authentication: Alternative Scramble Seed Reset and_Alternative Framing
2 work modes: connect 27MHz crystal， inject 27MHz clock
DAC connection detection supported
DP input detection supported
Support Auto Power Saving mode and_low stand-by current
Support Spread Spectrum Clocking (de-spreading) for EMI reduction
DP AUX channel and_IIC slave interface are available for firmware update_and_debug
Low power architecture
3.3V/1.05V power supply supported for motherboard solution design
RoHS compliant and_Halogen free package
Offered in 40-Pin QFN package (5 x 5 mm) 服务保证
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