High-Performance Floating-Point Digital Signal Processor (DSP): – TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS – TMS320C31-60 (5 V) 33-ns Instruction Cycle Time 330 MOPS, 60 MFLOPS, 30 MIPS – TMS320C31-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS – TMS320C31-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320LC31-40 (3.3 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320LC31-33 (3.3 V) 60-ns Instruction Cycle Time 183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS 32-Bit High-Performance CPU 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations 32-Bit Instruction Word, 24-Bit Addresses Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Boot-Program Loader On-Chip Memory-Mapped Peripherals: – One Serial Port – Two 32-Bit Timers – One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation Fabricated Using 0.6 μm Enhanced Performance Implanted CMOS (EPIC?) Technology by Texas Instruments (TI?) 132-Pin Plastic Quad Flat Package (PQ Suffix) Eight Extended-Precision Registers Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes Two- and Three-Operand Instructions Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support Bus-Control Registers Configure Strobe-Control Wait-State Generation
description The TMS320C31 and TMS320LC31 DSPs are 32-bit, floating-point processors manufactured in 0.6 μm triple-level-metal CMOS technology. The TMS320C31 and TMS320LC31 are part of the TMS320C3x generation of DSPs from Texas Instruments. The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The TMS320C3x optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The TMS320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.
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