IMXRT1040CEC中文资料恩智浦数据手册PDF规格书

1.1

Features

The i.MX RT1040 processors are based on Arm Cortex-M7 Core Platform, which has the following features:

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Supports single Arm Cortex-M7 Core with:

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32 KB L1 Instruction Cache

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32 KB L1 Data Cache

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Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture

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Support the Armv7-M Thumb instruction set

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Integrated MPU, up to 16 individual protection regions

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Tightly coupled GPIOs, operating at the same frequency as Arm Core

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Up to 512 KB I-TCM and D-TCM in total

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Frequency of 600 MHz

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Cortex M7 CoreSight™ components integration for debug

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Frequency of the core, as per Table 9.

The SoC-level memory system consists of the following additional components:

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Boot ROM (128 KB)

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On-chip RAM (512 KB)

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512 KB OCRAM shared between ITCM/DTCM and OCRAM

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External memory interfaces:

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8/16-bit SDRAM, up to SDRAM-133/SDRAM-166

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8/16-bit SLC NAND FLASH, with ECC handled in software

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SD/eMMC

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SPI NOR/NAND FLASH

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Parallel NOR FLASH with XIP support

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Two single/dual channel Quad SPI FLASH with XIP support

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Timers and PWMs:

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Two General Programmable Timers (GPT)

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4-channel generic 32-bit resolution timer for each

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Each support standard capture and compare operation

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Four Periodical Interrupt Timers (PIT)

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Generic 32-bit resolution timer

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Periodical interrupt generation

Four Quad Timers (QTimer)

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4-channel generic 16-bit resolution timer for each

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Each support standard capture and compare operation

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Quadrature decoder integrated

Four FlexPWMs

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Up to 8 individual PWM channels per each

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16-bit resolution PWM suitable for Motor Control applications

Four Quadrature Encoder/Decoders