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IDT72V3640L7.5PF中文资料3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO数据手册Renesas规格书

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厂商型号

IDT72V3640L7.5PF

功能描述

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

制造商

Renesas Renesas Technology Corp

中文名称

瑞萨 瑞萨科技有限公司

数据手册

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更新时间

2025-9-27 10:31:00

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IDT72V3640L7.5PF规格书详情

描述 Description

DESCRIPTION:
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is
   written to an empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 MbitFEATURES:
• Choose among the following memory organizations:Commercial
   IDT72V3640 - 1,024 x 36
   IDT72V3650 - 2,048 x 36
   IDT72V3660 - 4,096 x 36
   IDT72V3670 - 8,192 x 36
   IDT72V3680 - 16,384 x 36
   IDT72V3690 - 32,768 x 36
   IDT72V36100 - 65,536 x 36
   IDT72V36110 - 131,072 x 36
• 133 MHz operation (7.5 ns read/write cycle time)
• User selectable input and output port bus-sizing
   - x36 in to x36 out
   - x36 in to x18 out
   - x36 in to x9 out
   - x18 in to x36 out
   - x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
   default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost
   Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
   Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
   simultaneously)
• Available in the 128-pin Thin Quad Flat Pack (TQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available

供应商 型号 品牌 批号 封装 库存 备注 价格
IDT
05+
原厂原装
4228
只做全新原装真实现货供应
询价
IDT
22+
144PBGA
9000
原厂渠道,现货配单
询价
IDT
23+
128TQFP
9526
询价
IDT
24+
QFP
4100
郑重承诺只做原装进口现货
询价
IDT
2402+
TQFP
8324
原装正品!实单价优!
询价
IDT
22+
BGA
5000
全新原装现货!自家库存!
询价
IDT
25+
QFP
3600
大量现货库存,提供一站式服务!
询价
IDT
14+
BGA144
1500
全新进口原装
询价
IDT
1922+
BGA
8200
莱克讯原厂货源每一片都来自原厂原装现货薄利多
询价
IDT
25+
QFP
6500
独立分销商 公司只做原装 诚心经营 免费试样正品保证
询价