CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM

DESCRIPTION: The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is

文件：72.5 Kbytes 页数：7 Pages

IDT

CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM

DESCRIPTION: The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is

文件：72.5 Kbytes 页数：7 Pages

IDT

CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM

DESCRIPTION: The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is

文件：72.5 Kbytes 页数：7 Pages

IDT

CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM

DESCRIPTION: The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is

文件：72.5 Kbytes 页数：7 Pages

IDT