IDT5T9891集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

FEATURES:

• 2.5 VDD

• 6 pairs of programmable skew outputs

• Low skew: 100ps all outputs at same interface level, 250ps all

outputs at different interface levels

• Selectable positive or negative edge synchronization

• Tolerant of spread spectrum input clock

• Synchronous output enable

• Selectable inputs

• Input frequency: 4.17MHz to 250MHz

• Output frequency: 12.5MHz to 250MHz

• Internal non-volatile EEPROM

• JTAG or I2C bus serial interface for programming

• Hot insertable and over-voltage tolerant inputs

• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)

• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input

interface

• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for

each output bank

• Selectable differential or single-ended inputs and six differential outputs

• PLL bypass for DC testing

• External differential feedback, internal loop filter

• Low Jitter: <75ps cycle-to-cycle, all outputs at same interface

level: <100ps cycle-to-cycle all outputs at different interface levels

• Power-down mode

• Lock indicator

• Available in VFQFPN package