3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is

文件：132.46 Kbytes 页数：10 Pages

IDT