28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle

文件：539.08 Kbytes 页数：22 Pages

IDT

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle

文件：538.99 Kbytes 页数：22 Pages

IDT

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL

Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 176-ball LFBGA package

文件：686.88 Kbytes 页数：22 Pages

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28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle

文件：538.99 Kbytes 页数：22 Pages

IDT