14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers optimized to drive the DDR2 DIMM

文件：498.62 Kbytes 页数：21 Pages

IDT

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Features • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50 more dynamic driver strength than standard SSTU32864 • Supports LVCMOS switching levels on C1 and RESET inputs • Low voltage operation: VDD = 1.7V

文件：693.95 Kbytes 页数：21 Pages

RENESAS

瑞萨

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Features • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50 more dynamic driver strength than standard SSTU32864 • Supports LVCMOS switching levels on C1 and RESET inputs • Low voltage operation: VDD = 1.7V

文件：693.95 Kbytes 页数：21 Pages

RENESAS

瑞萨

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers optimized to drive the DDR2 DIMM

文件：498.62 Kbytes 页数：21 Pages

IDT