ICS9LPRS525集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

Recommended Application:

56-pin CK505 compatible clock, w/fully integrated Vreg and series

resistors on differential outputs

Output Features:

• 2 - CPU differential low power push-pull pairs

• 7 - SRC differential push-pull pairs

• 1 - CPU/SRC selectable differential low power push-pull pair

• 1 - SRC/DOT selectable differential low power push-pull pair

• 1 - SRC/SE selectable differential push-pull pair/Single-ended

outputs

• 5 - PCI, 33MHz

• 1 - USB, 48MHz

• 1 - REF, 14.318MHz

Key Specifications:

• CPU outputs cycle-cycle jitter <85ps

• SRC output cycle-cycle jitter <85ps

• PCI outputs cycle-cycle jitter <250ps

• +/- 100ppm frequency accuracy on all outputs

• SRC outputs meet PCIe Gen2 when sourced from PLL3