ICS9LP505-1中文资料瑞萨数据手册PDF规格书

Output Features:

• 2 - CPU differential low power push-pull pairs

• 10 - SRC differential low power push-pull pairs

• 1 - CPU/SRC selectable differential low power push-pull pair

• 1 - SRC/DOT selectable differential low power push-pull pair

• 5 - PCI, 33MHz

• 1 - PCI_F, 33MHz free running

• 1 - USB, 48MHz

• 1 - REF, 14.318MHz

Key Specifications:

• CPU outputs cycle-cycle jitter < 85ps

• SRC output cycle-cycle jitter < 125ps

• PCI outputs cycle-cycle jitter < 500ps

• +/- 100ppm frequency accuracy on CPU & SRC clocks

Features/Benefits:

• Supports spread spectrum modulation, default is 0.5 down spread

• Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning

• Selectable SRC differential push-pull pair/two single-ended outputs