ICS9FG1901YKLF-T中文资料瑞萨数据手册PDF规格书

Recommended Application:

DB1900G: CPU Host Bus, PCI Express and Fully-Buffered

DIMM clocking

Features:

• Power up default is all outputs in 1:1 mode

• DIF_(16:0) can be “gear-shifted” from the input CPU

Host Clock

• DIF_(18:17) can be “gear-shifted” from the input CPU

Host Clock

• Spread spectrum compatible

• Supports output clock frequencies up to 400 MHz

• 8 Selectable SMBus addresses

• SMBus address determines PLL or Bypass mode

• VDDA controlled power down mode