ICS97ULP845A中文资料瑞萨数据手册PDF规格书

Recommended Application:

• DDR2 Memory Modules / Zero Delay Buffer Fan Out

• Provides complete DDR DIMM logic solution

Product Description/Features:

• Low skew, low jitter PLL clock driver

• 1 to 5 differential clock distribution (SSTL_18)

• Feedback pins for input to output synchronization

• Spread Spectrum tolerant inputs

• Auto PD when input signal is at a certain logic state

Switching Characteristics:

• Period jitter: 40ps

• Half-period jitter: 60ps

• CYCLE - CYCLE jitter 40ps

• OUTPUT - OUTPUT skew: 40ps