ICS93725YFT中文资料ICST数据手册PDF规格书

Product Description/Features:

• Low skew, Zero Delay Buffer

• 1 to 13 SDRAM PC133 clock distribution

• 1 to 6 pairs of DDR clock distribution

• I2C for functional and output control

• Separate feedback path for both memory mode to adjust synchronization.

• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs

• Frequency support for up to 200MHz

• Individual I2C clock stop for power mananagement

• CMOS level control signal input

Recommended Application:

DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/650 & 735/740/746 style chipsets.