ICS93725中文资料瑞萨数据手册PDF规格书

Product Description/Features:

• Low skew, Zero Delay Buffer

• 1 to 13 SDRAM PC133 clock distribution

• 1 to 6 pairs of DDR clock distribution

• I2C for functional and output control

• Separate feedback path for both memory mode to adjust synchronization.

• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs

• Frequency support for up to 200MHz (DDR 400)

• Individual I2C clock stop for power mananagement

• CMOS level control signal input

Switching Characteristics:

• OUTPUT - OUTPUT skew: <100ps

• Output Rise and Fall Time for DDR outputs: 550ps - 1150ps

• DUTY CYCLE: 47 - 53