DDR Phase Lock Loop Zero Delay Clock Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2 C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

文件：343.38 Kbytes 页数：9 Pages

RENESAS

瑞萨

DDR Phase Lock Loop Zero Delay Clock Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Recommended Application: DDR Zero Delay Clock Buffer

文件：65.84 Kbytes 页数：7 Pages

ICST

DDR Phase Lock Loop Zero Delay Clock Buffer

Renesas

瑞萨

DDR Phase Lock Loop Zero Delay Clock Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2 C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

文件：343.38 Kbytes 页数：9 Pages

RENESAS

瑞萨

DDR Phase Lock Loop Zero Delay Clock Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Recommended Application: DDR Zero Delay Clock Buffer

文件：65.84 Kbytes 页数：7 Pages

ICST