245 MHz Clock Generator and Integrated Buffer for PowerPC

General Description The ICS9178-03 generates all clocks required for high speed PowerPC RISC microprocessor systems. Generating clocks in phase with an external reference frequency allows the ICS9178-03 to be used as a multiplying zero delay buffer. Three different multiplying factors are externa

文件：526.79 Kbytes 页数：8 Pages

ICST

245 MHz Clock Generator and Integrated Buffer for PowerPC

General Description The ICS9178-03 generates all clocks required for high speed PowerPC RISC microprocessor systems. Generating clocks in phase with an external reference frequency allows the ICS9178-03 to be used as a multiplying zero delay buffer. Three different multiplying factors are externa

文件：526.79 Kbytes 页数：8 Pages

ICST

245 MHz Clock Generator and Integrated Buffer for PowerPC

Renesas

瑞萨

AM Receiver IC

DESCRIPTION The MAS9178 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automa

文件：139.9 Kbytes 页数：8 Pages

MAS

Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout

General Description The MAX9178 quad low-voltage differential signaling (LVDS) line driver with high-ESD tolerance is ideal for applications requiring high data rates and low power with reduced noise. The MAX9178 is guaranteed to transmit data at speeds up to 400Mbps (200MHz) over controlled impe

文件：310.14 Kbytes 页数：14 Pages

Maxim

美信

Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout

General Description The MAX9178 quad low-voltage differential signaling (LVDS) line driver with high-ESD tolerance is ideal for applications requiring high data rates and low power with reduced noise. The MAX9178 is guaranteed to transmit data at speeds up to 400Mbps (200MHz) over controlled impe

文件：310.14 Kbytes 页数：14 Pages

Maxim

美信