One LVDS output pair

文件：767.45 Kbytes 页数：15 Pages

IDT

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

文件：485.06 Kbytes 页数：16 Pages

RENESAS

瑞萨

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

文件：485.06 Kbytes 页数：16 Pages

RENESAS

瑞萨

4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination

Features • High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, S

文件：485.06 Kbytes 页数：16 Pages

RENESAS

瑞萨