Low Skew, 1-to-8, Differential-to-LVDS Clock

文件：761.63 Kbytes 页数：16 Pages

IDT

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias netw

文件：539.82 Kbytes 页数：17 Pages

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Low Skew, 1-to-8 , Different ial-to-LVDS Clock

文件：299.2 Kbytes 页数：16 Pages

IDT

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features • Eight differential LVDS output pairs • One differential clock input pair • CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to

文件：635.03 Kbytes 页数：17 Pages

RENESAS

瑞萨