ICS851S201I中文资料瑞萨数据手册PDF规格书

特性 Features

• Two differential HCSL output pairs

• Two selectable differential clock input pairs

• CLKx, nCLKx pairs can accept HCSL level inputs

• Low level input detection on selected input (latched)

• Maximum Input frequency: 250MHz

• Output skew: 5ps (typical)

• Propagation delay: 1.4ns (typical)

• Additive RMS phase jitter at 133.33MHz (12kHz - 20MHz):

0.151ps (typical)

• Full 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging