Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

文件：1.09248 Mbytes 页数：27 Pages

RENESAS

瑞萨

Clock Generator for Cavium Processors

文件：885.75 Kbytes 页数：26 Pages

IDT

Clock Generator for Cavium Processors

文件：885.75 Kbytes 页数：26 Pages

IDT

Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

文件：1.09248 Mbytes 页数：27 Pages

RENESAS

瑞萨

Clock Generator for Cavium Processors

Features • One selectable differential LVPECL output pair for DDR 533/400/667 • Six LVCMOS/ LVTTL outputs, 15Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock re

文件：1.09248 Mbytes 页数：27 Pages

RENESAS

瑞萨