ICS8344BYI-T中文资料ICST数据手册PDF规格书

GENERAL DESCRIPTION

The ICS8344I is a low voltage, low skew fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344I has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344I is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. ICS8344I is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes.

FEATURES

• 24 LVCMOS outputs, 7Ω typical output impedance

• 2 selectable differential clock input pairs for redundant clock applications

• CLKx, nCLKx pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency up to 100MHz

• Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input

• Multiple output enable pins for disabling unused outputs in reduced fanout applications

• Output skew: 275ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Bank skew: 150ps (maximum)

• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes

• -40°C to 85°C ambient operating temperature