ICS670M-01T集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Description

The ICS670-01 is a high speed, low phase noise Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of ICS’ ClockBlocks™ family, the zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs, giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin.

Features

• Packaged in 16 pin SOIC

• Clock inputs from 5 to 160 MHz (see page 2)

• Patented PLL with the lowest phase noise

• Output clocks up to 160 MHz at 3.3 V

• 15 selectable on-chip multipliers

• Power down mode available

• Low phase noise: -124 dBc/Hz at 10 kHz

• Output Enable function tri-states outputs

• Low jitter 15 ps one sigma

• Full swing CMOS outputs with 25 mA drive capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• 3.3 V or 5 V operation