Networking Clock Source

Description The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking ch

文件：156.21 Kbytes 页数：6 Pages

ICST

Networking Clock Source

Description The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking ch

文件：156.21 Kbytes 页数：6 Pages

ICST

Networking Clock Source

Description The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking ch

文件：156.21 Kbytes 页数：6 Pages

ICST

NETWORKING CLOCK SOURCE

Features • Packaged in 20-pin (150 mil) SSOP (QSOP) • Pb (lead) free package, RoHS compliant • 12.5 MHz or 25 MHz fundamental crystal or clock input • Six output clocks with selectable frequencies • SDRAM frequencies of 67, 83, 100, and 133 MHz • Buffered crystal reference output • Zero ppm

文件：391.75 Kbytes 页数：8 Pages

RENESAS

瑞萨

Networking Clock Source

Description The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking ch

文件：156.21 Kbytes 页数：6 Pages

ICST

NETWORKING CLOCK SOURCE

Description The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking ch

文件：207.52 Kbytes 页数：7 Pages

IDT