LOW PHASE NOISE CLOCK MULTIPLIER

Description\nThe ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10 - 27 • Fully integrated PLL, no external loop filter required\n• Differential 3.3 V LVPECL outputs\n• Uses fundamental 10 - 27 MHz crystal or clock\n• Output clocks up to 220 MHz at 3.3 V\n• Low phase noise: -122 dBc/Hz at 10 kHz\n• Low jitter - 15 ps one sigma typ.\n• Powerdown mode lowers power consump;

Renesas

瑞萨

LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10 -

文件：139.16 Kbytes 页数：6 Pages

ICST

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK MULTIPLIER 16-TSSOP

Renesas Electronics America Inc

LOW PHASE NOISE CLOCK MULTIPLIER

Features • Fully integrated PLL, no external loop filter required • Differential 3.3 V LVPECL outputs • Uses fundamental crystal or clock — Crystal input frequency: 10 to 27MHz — Clock input: 10 to 38MHz (mulitply by 6) 10 to 31MHz (all other multiply settings) • Output clocks up to 230 MHz

文件：273.52 Kbytes 页数：9 Pages

RENESAS

瑞萨

LOW PHASE NOISE CLOCK MULTIPLIER

Features • Fully integrated PLL, no external loop filter required • Differential 3.3 V LVPECL outputs • Uses fundamental crystal or clock — Crystal input frequency: 10 to 27MHz — Clock input: 10 to 38MHz (mulitply by 6) 10 to 31MHz (all other multiply settings) • Output clocks up to 230 MHz

文件：273.52 Kbytes 页数：9 Pages

RENESAS

瑞萨

LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10 -

文件：139.16 Kbytes 页数：6 Pages

ICST