ICS527R-02T集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Description

The ICS527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz.

Features

• Packaged as 28-pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• PECL IN to CMOS OUT

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency—no software needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz to 200 MHz

• Output clock frequencies from 2.5 MHz to 160 MHz

• Very low jitter

• Duty cycle of 45/55

• Operating voltage of 3.3 V

• Advanced, low-power CMOS process

• Industrial temperature version available