ICS507M-01T集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce output clocks up to 200 MHz.

特性 Features

• Packaged as 16 pin narrow SOIC or die

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 5 - 52 MHz

• Uses low-cost crystal

• Differential PECL output clock frequencies up

to 200 MHz

• Duty cycle of 49/51

• 3.3 V or 5.0 V±10 operating supply

• Ideal for SONET applications and oscillator

manufacturers

• Advanced, low power CMOS process

• Industrial temperature versions available