3.3V Phase-Lock Loop Clock Driver

General Description The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2509C operates

文件：248.21 Kbytes 页数：7 Pages

ICST

HALF-BRIDGE DRIVER

文件：628.11 Kbytes 页数：21 Pages

IRF

MJ-2509N

文件：56.53 Kbytes 页数：1 Pages

ETC1List of Unclassifed Manufacturers

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2.5 MM AUDIO JACK

文件：295.16 Kbytes 页数：3 Pages

CUI