IC61S51218T-166TQ中文资料ICSI数据手册PDF规格书

DESCRIPTION

ICSIs 8Mb SyncBurst Pipelined SRAMs integrate a 512k x 18, 256k x 32, or 256k x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

FEATURES

• Pipeline Mode operation

• Single/Dual Cycl Deselect

• User-selectable Output Drive Strength with XQ Mode

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and control

• Pentium™ or linear burst sequence control using MODE input

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and 119-pin PBGA package

• Single +3.3V, +10, –5 core power supply

• Power-down snooze mode

• 2.5V or 3.3V I/O Supply

• Snooze MODE for reduced-power standby

• T version (three chip selects)

• D version (two chip selects)