512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

DESCRIPTION ICSIs 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. FEATURES

文件：764.14 Kbytes 页数：78 Pages

ICSI

512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

DESCRIPTION ICSIs 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. FEATURES

文件：764.14 Kbytes 页数：78 Pages

ICSI

512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

DESCRIPTION ICSIs 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. FEATURES

文件：764.14 Kbytes 页数：78 Pages

ICSI

512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

DESCRIPTION ICSIs 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. FEATURES

文件：764.14 Kbytes 页数：78 Pages

ICSI