HYMP512U64P8-E3/C4数据手册SK hynix中文资料规格书

描述 Description

This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in133.35mm width form factor of industry standard. It is suitable for easy interchange and addition.FEATURES
• JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
•4 Bank architecture
•Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)

特性 Features

• JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
•4 Bank architecture
•Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)