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HY57V121620LT-K中文资料PDF规格书
HY57V121620LT-K规格书详情
DESCRIPTION
The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.
HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by UDQM, LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 8192 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
产品属性
- 型号:
HY57V121620LT-K
- 制造商:
HYNIX
- 制造商全称:
Hynix Semiconductor
- 功能描述:
4 Banks x 8M x 16Bit Synchronous DRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
Hynix/SK hynix/海力士/海力士半 |
21+ |
TSOP |
103 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
HYNIX |
19718+ |
9750 |
进品原装正品 现货库存带17%增值发票 |
询价 | |||
2023+ |
SOP |
80000 |
一级代理/分销渠道价格优势 十年芯程一路只做原装正品 |
询价 | |||
HYNIX/海力士 |
23+ |
TSOP-54 |
68600 |
原装现货 |
询价 | ||
收购IC |
1525+ |
TSOP-54 |
5083 |
长期现金收购原装IC |
询价 | ||
HYNIX |
23+ |
NA |
3230 |
航宇科工半导体-中国航天科工集团战略合作伙伴! |
询价 | ||
HYNIX |
20+/21+ |
TSOP |
6956 |
SDRAM全新原装进口 |
询价 | ||
HY |
09+ |
SSOP |
8 |
询价 | |||
HYNIX |
1011 |
15 |
公司优势库存 热卖中! |
询价 | |||
HY |
2022+ |
SSOP |
8 |
原厂原装,假一罚十 |
询价 |