HT9480中文资料合泰数据手册PDF规格书

General Description

The HT9480 is a high performance pager controller. The built-in single cycle instructions (16-bit wide) and two-stage pipeline architecture of the HT9480 account for its high performance. The controller contains a full function pager decoder (POCSAG code) at 512, 1200, or 2400 bits per second data rate and an LCD display driver with a 35x4 dot output.

特性 Features

• Operating voltage: 2.4V~3.3V

• Low power crystal oscillator control

- 512, 1200, or 2400 bps data rate operation

• Decodes CCIR Radio-paging Code No.1 (POCSAG Code)

• 2-bit random and optional 4-bit burst error correction

• Improved synchronization algorithm

• Supports up to 6 independently programmable user addresses and 6 user frames

• Three RF power on timing control pins

• Single crystal for all available baud rate (76.8kHz crystal)

• Battery low indication (external detector)

• Battery fail interrupt and data ready interrupt

• 8Kx16 program ROM

• 416x8 data RAM

• 35x4 LCD display

• 7 input lines and 10 bidirectional I/O lines

• 8-bit programmable timer for RTC interrupt

• 8-bit programmable timer/event counter and overflow interrupt

• 8-bit programmable tone generator with buzzer output

• Watchdog Timer

• HALT function and wake-up feature reduce power consumption

• 63 powerful instructions, most instructions in one machine cycle

• Eight-level subroutine nesting

• Table read instruction

• Inverted or non-inverted input signal selection for decoder input

• 80-pin LQFP(12x12) package