HM64YGB36100中文资料瑞萨数据手册PDF规格书

Description

The HM64YGB36100 is a synchronous fast static RAM organized as 1-Mword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA.

Features

• 2.5 V ± 5 operation and 1.5 V (VDDQ)

• 32-Mbit density

• Synchronous register to register operation

• Internal self-timed late write

• Byte write control (4 byte write selects, one for each 9-bit)

• Optional ×18 configuration

• HSTL compatible I/O

• Programmable impedance output drivers

• Differential HSTL clock inputs

• Asynchronous G output control

• Asynchronous sleep mode

• FC-BGA 119pin package with SRAM JEDEC standard pinout

• Limited set of boundary scan JTAG IEEE 1149.1 compatible