4 M SRAM (512-kword x 8-bit)

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II i

文件：80.99 Kbytes 页数：16 Pages

HitachiHitachi Semiconductor

日立日立公司

4 M SRAM (512-kword 쨈 8-bit)

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II i

文件：99.16 Kbytes 页数：18 Pages

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瑞萨

4 M SRAM (512-kword x 8-bit)

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II i

文件：80.99 Kbytes 页数：16 Pages

HitachiHitachi Semiconductor

日立日立公司

4 M SRAM (512-kword 쨈 8-bit)

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II i

文件：99.16 Kbytes 页数：18 Pages

RENESAS

瑞萨

4 M SRAM (512-kword x 8-bit)

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II i

文件：80.99 Kbytes 页数：16 Pages

HitachiHitachi Semiconductor

日立日立公司

4 M SRAM (512-kword 쨈 8-bit)

Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II i

文件：99.16 Kbytes 页数：18 Pages

RENESAS

瑞萨