HM5264805FTT-A60中文资料美光科技数据手册PDF规格书

Description

The HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The HM5264405F is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features

• 3.3 V power supply

• Clock frequency: 133 MHz/100 MHz (max)

• LVTTL interface

• Single pulsed RAS

• 4 banks can operate simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length: 1/2/4/8/full page

• 2 variations of burst sequence

- Sequential (BL = 1/2/4/8/full page)

- Interleave (BL = 1/2/4/8)

• Programmable CAS latency: 2/3

• Byte control by DQM:DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F)

• Refresh cycles: 4096 refresh cycles/64 ms

• 2 variations of refresh

- Auto refresh

- Self refresh

• Full page burst length capability

- Sequential burst

- Burst stop capability