HM3-6514S-9中文资料INTERSIL数据手册PDF规格书

Description

The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation.

On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays.

Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time.

Data retention supply voltage and supply current are guaran teed over temperature.

Features

• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max

• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min

• TTL Compatible Input/Output

• Common Data Input/Output

• Three-State Output

• Standard JEDEC Pinout

• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max

• 18 Pin Package for High Density

• On-Chip Address Register

• Gated Inputs - No Pull Up or Pull Down Resistors Required