AD8131ARM

Marking：HJA；Package：MSOP；Low Cost, High Speed Differential Driver

FEATURES Highspeed 400MHz,−3dBfullpowerbandwidth 2000V/μsslewrate Fixedgainof2withnoexternalcomponents Internalcommon-modefeedbacktoimprovegainandphase balance:−60dB@10MHz Separateinputtosetthecommon-modeoutputvoltage Lowdistortion:68dBSFDR@5MHz2

AD8131ARM-REEL

Marking：HJA；Package：MSOP；Low Cost, High Speed Differential Driver

FEATURES Highspeed 400MHz,−3dBfullpowerbandwidth 2000V/μsslewrate Fixedgainof2withnoexternalcomponents Internalcommon-modefeedbacktoimprovegainandphase balance:−60dB@10MHz Separateinputtosetthecommon-modeoutputvoltage Lowdistortion:68dBSFDR@5MHz2

AD8131ARM-REEL7

Marking：HJA；Package：MSOP；Low Cost, High Speed Differential Driver

FEATURES Highspeed 400MHz,−3dBfullpowerbandwidth 2000V/μsslewrate Fixedgainof2withnoexternalcomponents Internalcommon-modefeedbacktoimprovegainandphase balance:−60dB@10MHz Separateinputtosetthecommon-modeoutputvoltage Lowdistortion:68dBSFDR@5MHz2

AD8131ARMZ

Marking：HJA；Package：MSOP；Low Cost, High Speed Differential Driver

FEATURES Highspeed 400MHz,−3dBfullpowerbandwidth 2000V/μsslewrate Fixedgainof2withnoexternalcomponents Internalcommon-modefeedbacktoimprovegainandphase balance:−60dB@10MHz Separateinputtosetthecommon-modeoutputvoltage Lowdistortion:68dBSFDR@5MHz2

AD8131ARMZ-REEL

Marking：HJA；Package：MSOP；Low Cost, High Speed Differential Driver

FEATURES Highspeed 400MHz,−3dBfullpowerbandwidth 2000V/μsslewrate Fixedgainof2withnoexternalcomponents Internalcommon-modefeedbacktoimprovegainandphase balance:−60dB@10MHz Separateinputtosetthecommon-modeoutputvoltage Lowdistortion:68dBSFDR@5MHz2

AD8131ARMZ-REEL7

Marking：HJA；Package：MSOP；Low Cost, High Speed Differential Driver

FEATURES Highspeed 400MHz,−3dBfullpowerbandwidth 2000V/μsslewrate Fixedgainof2withnoexternalcomponents Internalcommon-modefeedbacktoimprovegainandphase balance:−60dB@10MHz Separateinputtosetthecommon-modeoutputvoltage Lowdistortion:68dBSFDR@5MHz2

CD74HC112PWR

Marking：HJ112；Package：TSSOP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput

CD74HC112PWRE4

Marking：HJ112；Package：TSSOP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput

CD74HC137PW

Marking：HJ137；Package：TSSOP；High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features •SelectOneofEightDataOutputs -ActiveLowforCD74HC137andCD74HCT137 -ActiveHighfor’HC237andCD74HCT237 •l/OPortorMemorySelector •TwoEnableInputstoSimplifyCascading •TypicalPropagationDelayof13nsatVCC=5V, 15pF,TA=25oC(CD74HC237) •Fanout(Over

CD74HC137PWR

Marking：HJ137；Package：TSSOP；High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features •SelectOneofEightDataOutputs -ActiveLowforCD74HC137andCD74HCT137 -ActiveHighfor’HC237andCD74HCT237 •l/OPortorMemorySelector •TwoEnableInputstoSimplifyCascading •TypicalPropagationDelayof13nsatVCC=5V, 15pF,TA=25oC(CD74HC237) •Fanout(Over