Triple 10-Bit, 50 MSPS,3-Channel D/A Converter

Description The HI2309 is a triple 10-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 10-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational

文件：652.49 Kbytes 页数：9 Pages

INTERSIL

Triple 10-Bit, 50 MSPS,3-Channel D/A Converter

Renesas

瑞萨

Triple 10-Bit, 50 MSPS,3-Channel D/A Converter

Description The HI2309 is a triple 10-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 10-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational

文件：652.49 Kbytes 页数：9 Pages

INTERSIL

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

文件：135.34 Kbytes 页数：10 Pages

IDT

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain con

文件：295.07 Kbytes 页数：20 Pages

MAXIM

美信

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain con

文件：295.07 Kbytes 页数：20 Pages

MAXIM

美信