HEF4520BT-Q100数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The HEF4520B-Q100 is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous master reset input (nMR).
The counter advances on either the LOW-to-HIGH transition of the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter while the other clock input may be used as a clock enable input. Schmitt trigger action makes the clock input highly tolerant of slower clock rise and fall times. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 3)
• Specified from -40 °C to +85 °C

• Tolerant of slow clock rise and fall times
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Complies with JEDEC standard JESD 13-B