HEF4094B-Q100中文资料安世数据手册PDF规格书

1. General description

The HEF4094B-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register

and 3-state outputs. Both the shift and storage register have separate clocks. The device features

a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the

LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions

of the CP input to allow cascading when clock edges are fast. The same data is available at QS2

on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.

The data in the shift register is transferred to the storage register when the STR input is HIGH.

Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.

A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE

input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of

current limiting resistors to interface inputs to voltages in excess of VDD.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

• Fully static operation

• 5 V, 10 V, and 15 V parametric ratings

• Wide supply voltage range from 3.0 V to 15.0 V

• CMOS low power dissipation

• High noise immunity

• Standardized symmetrical output characteristics

• Complies with JEDEC standard JESD 13-B

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V